Semiconductor device and fabrication method for the same

ABSTRACT

A method of fabrication a semiconductor device characerized by: mounting a first semiconductor chip on a wiring substrate; bonding a spacer having a first main surface and a second main surface oppose to the first main surface so that the first main surface contact to the first semiconductor chip; and bonding a second semiconductor chip having a third main surface larger than the first main surface, onto the second main surface via a layer of a die bonding material selectively formed on a part of the third main surface.

CROSS-REFERENCE TO RELATED APPLICATION AND INCORPORATION BY REFERENCE

This application claims benefit of priority based on Japanese PatentApplications filed previously by the applicant, namely, Japanese PatentApplication Nos. 2004-048266 (filing date: Feb. 24, 2004), the contentsof which are herein incorporated by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device and afabrication method for the same.

2. Description of the Related Art

In recent years, thinner semiconductor chips are desired for mounting ina card-shaped thin package and providing a small mounted area ofmultiple semiconductor chips. However, wafer cracks or undersidechipping may occur when transferring or dicing individual semiconductorchips, which are obtained by dicing a thin wafer provided by grindingthe side (underside) opposing a device formed wafer side.

Dicing before grinding (DBG) methodology has been proposed as a methodof preventing, to the utmost, wafer cracks or underside chipping due tothinned semiconductor chips (see Japanese Patent Application Laid-open2002-118081, Japanese Patent Application Laid-open 2003-147300).

A semiconductor device 110 fabricated through the DBG methodology isshown in FIG. 1A, and a semiconductor device 120 is shown in FIG. 1B.The semiconductor device 110 shown in FIG. 1A is made up of a wiringsubstrate 106, a first and a second semiconductor chip 101 a and 101 b,a spacer 113, die bonding sheets (material) 104, and wires 112 a , 112 bconnected to the first and the second semiconductor chip 101 a and 101b. The first semiconductor chip 101 a mentioned above has the diebonding sheet 104 on a first main surface opposing the wiring substrate106, and a semiconductor element is formed on a second main surfaceopposing the first main surface. Accordingly, the second semiconductorchip 101 b mentioned above has the die bonding sheet 104 on a third mainsurface opposing the wiring substrate 106, and a semiconductor elementis formed on a fourth main surface opposing the third main surface. Thedie bonding sheet 104 having the same width as the spacer 113, which issandwiched between the first and the second semiconductor chip 101 a and101 b, is bonded to the first main surface opposing the wiring substrate106. The first semiconductor chip 101 a is mounted on the wiringsubstrate 106 via the die bonding sheet 104 formed on the first mainsurface. The second semiconductor chip 101 b is adhereed so that thethird main surface opposes the first semiconductor chip 101 a and thatthe spacer 113 is sandwiched therebetween.

A earlier technology fabrication method for the semiconductor device 110is explained forthwith while referencing the process drawings of FIG. 2Ato 2G and FIG. 3A to 3F.

-   (i) To begin with, as shown in FIG. 2A, semiconductor chips 101,    which are obtained by being divided into diced shapes through the    DBG methodology, are mounted on a surface protection sheet 102 so    that the device formation face (the first or the third main surface)    opposes the surface protection sheet 102.-   (ii) Next, the die bonding sheet 104 is mounted on the semiconductor    chips 101 as shown in FIG. 2B, and protruding portions 104 c of the    die bonding sheet 104 are removed as shown in FIG. 2C.-   (iii) After turning the die bonding sheet over as shown in FIG. 2D,    the die bonding sheet 104 is bonded on a sheet 108 so that the sheet    108 opposes the die bonding sheet 104. Afterwards, by peeling off    the surface protection sheet 102, the adhesion faces of the    respective semiconductor chips 101 are changed to the side of the    sheet 108, and are joined to the die bonding sheet 104.-   (iv) The semiconductor chip 101 with the die bonding sheet 104 is    irradiated with ultraviolet light using a earlier technology method    as shown in FIG. 2E. Consequently, an ultraviolet irradiated portion    of the die bonding material 104 b is hardened to be integrated with    the sheet 108. Meanwhile, the remaining portion of the die bonding    sheet 104 that was not irradiated since it is behind the    semiconductor chip 101 maintains viscosity that allows it to be    peeled off.-   (v) This allows only each semiconductor chip 101 with the die    bonding sheet 104 to be picked up when picking up the semiconductor    chip 101 in the direction of the arrow using a transfer collet (not    shown in the drawing) as shown in FIG. 2F.-   (vi) A semiconductor chip 101 is mounted as the first semiconductor    chip 101 a on the wiring substrate 106 via the die bonding sheet 104    as shown in FIG. 3A. A spacer 113 a is mounted on the first    semiconductor chip 101 a via the die bonding sheet 104 as shown in    FIG. 3B. At this time, the spacer 113 a with a predetermined width    is mounted so as to secure a clearance d between the first    semiconductor chip 101 a and the second semiconductor chip 101 b as    shown in FIG. 3D. This prevents the wire 112 a from being in contact    with the die bonding sheet 104 a during wire bonding, which is    explained later.-   (vii) The first semiconductor chip 101 a is bonded with a wire 112 a    as shown in FIG. 3C.-   (viii) The second semiconductor chip 101 b is mounted on the first    semiconductor chip 101 a via the spacer 113 a and the die bonding    sheet 104 as shown in FIG. 3D.-   (iv) The second semiconductor chip 101 b is bonded with a wire 112 b    as shown in FIG. 3E.-   (x) Afterwards, the semiconductor device 110 is fabricated as shown    in FIGS. 3F and 1A by encapusulating with a encapusulating material    111.

However, in the step of picking up each semiconductor chip 101 shown inFIG. 2F, it is not easy to peel the unhardened portion of the diebonding sheet 104 off the hardened portions 104 b of the die bondingsheet merged with the sheet 108. In other words, it is difficult to pickup selectively each semiconductor chip 101 adhered to the die bondingsheet 104.

To solve this problem, by a earlier technology, the semiconductor chip101 is pushed upwards from below the sheet 108 by a needle 114 or thelike as shown in FIG. 2G, thereby relaxing and allowing the sheet 108 tobe peeled off and then removing the hardened portions 104 b of the diebonding sheet.

Also, according to earlier technology, since it is difficult to controlthe location of the die bonding sheet 104, the die bonding sheet 104 isadhereed across the entire undersides (the first or the third mainsurfaces) of the semiconductor chips 101. As a result, the die bondingsheet 104 adhered to the underside of the second semiconductor chip 101b protrudes from the spacer 113 a, as shown in FIG. 3D. A thick spacer113 a is formed so as to prevent the wire 112 a from being in contactwith this protruding die bonding sheet 104 a. Consequently, the greaterthe number of wiring layers, the thicker the semiconductor device.

SUMMARY OF THE INVENTION

An aspect of the present invention is characterized by a method offabrication a semiconductor device including:

mounting a first semiconductor chip on a wiring substrate;

bonding a spacer having a first main surface and a second main surfaceoppose to the first main surface so that the first main surface contactto the first semiconductor chip; and

bonding a second semiconductor chip having a third main surface largerthan the first main surface, onto the second main surface via a layer ofa die bonding material selectively formed on a part of the third mainsurface.

Another aspect of the present invention is characterized by asemiconductor device including:

a wiring substrate; a first semiconductor chip mounted on the wiringsubstrate;

a spacer having a first main surface bonded onto the first semiconductorchip and a second main surface opposing to the main surface;

a die bonding material dipposed on the second main surface; and

a second semiconductor chip having a third main surface larger than thefirst main surface and a fourth main surface opposing the third mainsurface, and having the center of the third main surface bonded togetherwith the spacer so that the die bonding material is in contact with onlya part of the third main surface. The center of the third main surfaceis bonded together with the spacer so that the die bonding material canbe in contact with only a part of the third main surface.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A and 1B are schematic cross sections of a earlier technologysemiconductor device;

FIGS. 2A to 2G are schematic cross sections showing a earlier technologysemiconductor device fabrication method;

FIGS. 3A to 3F are schematic cross sections showing a earlier technologysemiconductor device fabrication method;

FIGS. 4A and 4B are schematic cross sections of a semiconductor deviceaccording to an embodiment of the present invention;

FIGS. 5A to 5C are schematic cross sections showing a fabrication methodusing the DBG methodology;

FIGS. 6A to 6E are schematic cross sections showing a semiconductordevice fabrication method according to an embodiment of the presentinvention;

FIGS. 7A to 7F are schematic cross sections showing a semiconductordevice fabrication method according to an embodiment of the presentinvention;

FIGS. 8A and 8B are enlargements of a part of a metallic mask to be usedfor a semiconductor device fabrication method according to an embodimentof the present invention;

FIGS. 9A, 9B, and 9C show a cross section (before die bonding) , theunderside (before die bonding), and the underside (after die bonding) ofa semiconductor chip with a die bonding material, respectively;

FIGS. 10A, 10B, and 10C show a cross section (before die bonding), theunderside (before die bonding), and the underside (after die bonding) ofa semiconductor chip with a die bonding material, respectively;

FIGS. 11A and 11B are enlargements of a part of a metallic mask to beused for a semiconductor device fabrication method according to amodification of an embodiment of the present invention;

FIGS. 12A, 12B, and 12C show a cross section (before die bonding), theunderside (before die bonding), and the underside (after die bonding) ofa semiconductor chip with a die bonding material, respectively;

FIGS. 13A, 13B, and 13C show a cross section (before die bonding), theunderside (before die bonding), and the underside (after die bonding) ofa semiconductor chip with a die bonding material, respectively;

FIGS. 14A and 14B are schematic cross sections of a semiconductor deviceaccording to a modification of an embodiment of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

The present invention is explained forthwith according to the followingembodiments; however, it is not limited thereto. Note that parts havingthe same or similar functions in the drawings are assigned the same orsimilar reference numerals, and descriptions thereof are omitted.

A semiconductor device 10 according to an embodiment of the presentinvention, as shown in FIG. 4A, includes: a wiring substrate 6; a firstsemiconductor chip 1 a mounted on the wiring substrate 6 via a diebonding material 4 a; a spacer 13 a having a first main surface bondedto the first semiconductor chip 1 a via the die bonding material 4 a; adie bonding material 4 c bonded to a second main surface opposing thefirst main surface of the spacer 13 a; and a second semiconductor chip 1b, which has a third main surface having a larger area than the firstmain surface of the spacer 13 a and a fourth main surface opposing thethird main surface.

Here, the die bonding material 4 c is bonded to the center of the thirdmain surface so that the spacer 13 a can be in contact with only a partof the third main surface of the second semiconductor chip 1 b. In thefirst and the second semiconductor chips 1 a and 1 b, semiconductorelements are merged on or in the second and the third main surfaceopposing the wiring substrate.

The semiconductor device 10 according to the embodiment includes wires12 a and 12 b bonded to the respective first and the secondsemiconductor chips 1 a and 1 b. It also has the semiconductor chips 1 aand 1 b mounted via the spacer 13 a, and the wires 12 a and 12 bencapusulated with an encapusulating material 11.

Material for the die bonding material 4 is not limited, and a earliertechnology die bonding material having characteristics needed for diebonding may be used as the die bonding material 4. A heat-hardening typeor an ultraviolet curing type may be used as the die bonding material 4;more specifically, a certain material having characteristics such aswettability and thixotropy to be suitably used for screen printing maybe preferable. Composition and viscosity of the die bonding material 4are selectable based on the knowledge of those skilled in the art. A diebonding material hardening (or half hardening) method may be selectedbased on a selected hardening type of the die bonding material 4.Heat-hardening or ultraviolet curing, for example, may be used as thehardening method. Note that either can be used.

A fabrication method for the semiconductor device 10 according to anembodiment is explained forthwith while referencing the DBG methodologyprocess drawings of FIG. 5 and fabrication process drawings of FIGS. 3and 4.

-   (i) A wafer 9 merging desired semiconductor elements formed on the    surface (a fourth main surface) is prepared. Recesses (grooves) 9 a,    which extend from the fourth main surface of the prepared wafer 9 to    a predetermined depth, are formed as shown in FIG. 5A. A surface    protection sheet 2 is affixed to the fourth main surface of the    wafer 9, as shown in FIG. 5B. Subsequently, the third main surface    of the wafer 9 to which the surface protection sheet 2 shown in FIG.    5B is affixed is ground so as to be divided into thinner pieces.    Consequently, thin dice-shaped semiconductor chips 1 shown in FIG.    5C, each of which may include minimal wafer cracks and underside    chipping due to thinness, are provided through the DBG methodology.-   (ii) A screen printing metallic mask 3 is disposed on the third main    surfaces of the semiconductor chips 1, as shown in FIG. 6A. Windows    are formed in this metallic mask 3 so that the die bonding material    4 can be applied to areas excluding the peripheral regions of the    second main surfaces of the semiconductor chips 1. This prevents the    die bonding material 4 from protruding from the semiconductor chips    1 in die bonding process. Afterwards, a squeegee 5 is moved in the    direction of the arrow, and the die bonding material 4 is applied on    the semiconductor chips 1 via the metallic mask 3, as shown in FIG.    6B. Through the above-described steps, almost the same shapes of die    bonding material 4 as those of the windows in the metallic mask 3    are delineated on the second main surfaces of the semiconductor    chips 1 as shown in FIG. 6C.-   (iii) Afterwards, the die bonding material 4 applied to the    semiconductor chips 1 is semi-hardened.-   (iv) After turning the semiconductor chip over adhering the    semiconductor chip to the sheet 8, the surface protection sheet 2 is    peeled off and the adhesion faces of the semiconductor chips 1 are    then changed to the sheet 8 as shown in FIG. 6D.-   (v) Afterwards, each semiconductor chip 1 adhered to the die bonding    material 4 captured using a transfer collet (not shown in the    drawings) or the like as shown in FIG. 6E.-   (vi) The held semiconductor chip 1 is mounted as the first    semiconductor chip la on the wiring substrate 6 via the die bonding    sheet 4 a as shown in FIG. 4A. When the semiconductor chip 1 is    mounted, the die bonding sheet 4 is melted and cured by heating or    the like.-   (vii) Subsequently, the die bonding material 4 b with the same width    as that of the spacer 13 a is applied to the first main surface of    the spacer 13 a through the above-described steps (i) to (vi)    according to the embodiment of the present invention. The resulting    spacer 13 a is mounted on the first semiconductor chip 1 a via the    die bonding material 4 b as shown in FIG. 7B.-   (viii) Afterwards, the first semiconductor chip 1 a is bonded with    the wire 12 a as shown in FIG. 7C.-   (iv) Subsequently, the die bonding material 4 c with the same width    as that of the spacer 13 a is applied on the first main surface of    the second semiconductor chip 1 b through the above-described    steps (i) to (vi) according to the embodiment of the present    invention. The resulting semiconductor chip 1 b is mounted on the    first semiconductor chip 1 a via the spacer 13 a and die bonding    materials 4 b and 4 c as shown in FIG. 7D. As a result, a unit U    having the spacer 13 a and the second semiconductor chip 1 b is    assembled on the semiconductor chip 1 a.-   (v) The wire 12 b is bonded to the second semiconductor chip 1 b as    shown in FIG. 7E.-   (vi) Afterwards, the semiconductor device 10 is fabricated as shown    in FIGS. 7F and 4A by encapusulating with an encapusulating material    111.

An applying position for the die bonding material 4 or a preferableshape of each window formed in the metallic mask 3 is explainedforthwith while referencing FIGS. 8A and 8B, FIGS. 9A and 9B and FIGS.10A and 10B.

FIG. 8A shows the metallic mask 3 in which a window 3 a is formed in aregion surrounded by visible curved outlines, each connecting adjacentapexes of a square semiconductor chip 1 indicated by a dashed line. Inother words, a bobbin-shaped window 3 a is formed having a widthnarrowing from the center of the semiconductor chip 1 towards each offour corners along approximately diagonal lines of the shape of thesemiconductor chip 1.

FIG. 8B shows the metallic mask 3 having a quadrilateral window 3 bsimilar to the shape of the semiconductor chip 1 except for theperipheral region thereof. FIGS. 9A, 9B, and 9C show a cross section ofthe semiconductor chip 1 having the die bonding material 4 (before diebonding), the underside thereof (before die bonding), and undersidethereof (after die bonding), respectively, fabricated using the metallicmask 3 shown in FIG. 8A. FIGS. 10A, 10B, and 10C show a cross section ofthe semiconductor chip 1 having the die bonding material 4 (before diebonding), the underside thereof (before die bonding), and undersidethereof (after die bonding), respectively, fabricated using the metallicmask 3 shown in FIG. 8B.

As shown in FIGS. 10A and 10B, the die bonding material 4 is applied onthe underside (first main surface) of the semiconductor chip 1 using themetallic mask 3 shown in FIG. 8B. As a result, when die bonding thesemiconductor chip 1, the wet die bonding material 4 spreads over theunderside of the semiconductor chip 1, as shown in FIG. 3C. The diebonding material 4 also runs out of the portions of the sides indicatedby broken lines, which do not include the four corners 1 c of thesemiconductor chip 1. Such corners 1 c where the die bonding material isunapplied may cause a drop in bonding reliability. Moreover, if thereare such portions running out of the semiconductor chip, it is necessaryto provide a space or clearance for the wiring so as to prevent thematerial from contaminating the wiring when mounting the semiconductorchip.

On the other hand, by selectively applying the die bonding material 4 ona region defined by curved lines 1 ₁, 1 ₂, 1 ₃, and 1 ₄ connecting theapexes A, B, C, and D of the shape of the square semiconductor chip 1and running the die bonding material into the inner area thereof asshown in FIG. 9B, there are no unapplied regions left when die bonding,and the protrusions of the die bonding material 4 can be minimized.

Since there are no regions, bonding reliability is improved. Moreover,due to the reduced amount of protrusions, the amount of die bondingmaterial 4 to be used is reduced. Furthermore, providing a clearance orspace becomes unnecessary for mounting the semiconductor chip or bondingwires. In other words, as compared to the earlier technologysemiconductor devices, a thin, mounted semiconductor device can befabricated.

As described above, it is preferable that the metallic mask 3 to be usedfor applying the die bonding material 4 has a window formed in a regiondefined by the curve lines 1 ₁, 1 ₂, 1 ₃, and 1 ₄ connecting adjacentones of the apexes A, B, C, and D of the polygon as shown in FIG. 8A.

According to the embodiment of the present invention described above,the step of removing protrusions of the die bonding sheet (material) canbe omitted. Moreover, since the positions of applying the die bondingmaterial can be controlled, the amount of the die bonding materialrunning out of a semiconductor chip which occurs when mounting the chipis considerably reduced. Consequently, a simplified fabrication processcan be provided, and the amount of die bonding material to be used isreduced. Furthermore, a minimal clearance required in the wire bondingstep can be attained.

Moreover, according to the embodiment of the present invention, thinnersemiconductor devices than the earlier technology devices can beprovided. In other words, in a earlier technology method, a die bondingsheet (material) 104 a is adhered to the third main surface of thesecond semiconductor chip 101 b as shown in FIG. 3D. Therefore, the diebonding material 104 a hangs out of the spacer 113 a. On the other hand,according to the embodiment of the present invention as shown in FIG.7D, die bonding materials 4 a and 4 b are formed on only portions incontact with the second semiconductor chip 1 b and the spacer 13 a,respectively. In other words, a clearance between semiconductor chipscan be provided without using a thick spacer 13 a. According to theembodiment of the present invention described above, a thin spacer 13 acan be formed, thereby providing a thin semiconductor device.

As shown in FIG. 4B, additional semiconductor chips 1 c and 1 d may bemounted between the first semiconductor chip 1 a and the wiringsubstrate 6.

A semiconductor device including two semiconductor chips is explainedaccording to the above-described embodiment. As shown in FIG. 4B,however, a semiconductor device 20 including four semiconductor chipscan be also fabricated by mounting additional semiconductor chips 1 viaspacers 13 using the aforementioned fabrication method according to theembodiment. In this manner, fabrication of multilayers by increasing thenumber of units, each being made from a semiconductor chip and a spacer,results in a thin semiconductor device.

An applying position for the die bonding material 4 or anotherpreferable shape of each window formed in the metallic mask 3 isexplained by referencing to FIGS. 11A and 11B, FIGS. 12A to 12C , 13A to13C ,and FIGS. 14A and 14B.

FIG. 11A shows the metallic mask 3 in which a window 3 c is formed in ashape similar to an X shape on the approximately diagonal lines of theshape of the semiconductor chip 1. FIG. 11B shows the metallic mask 3having windows 3 d 1 to 3 d 4 formed to pass through the center ofsemiconductor chip 1 and an end of the semiconductor chip 1. In otherwords, L shaped windows 3 d 1 to 3 d 4 are formed on the corners of thesemiconductor chip 1. FIGS. 12A to 12C show a cross section of thesemiconductor chip 1 having the die bonding material 4 (before diebonding), the underside thereof (before die bonding), and the undersidethereof (after die bonding), respectively, fabricated using the metallicmask 3 shown in FIG. 11A. FIGS. 13A to 13C show a cross section of thesemiconductor chip 1 having the die bonding material 4 (before diebonding), the underside thereof (before die bonding), and an undersidethereof (after die bonding), respectively, fabricated using the metallicmask 3 shown in FIG. 11B.

As shown in FIGS. 12A and 12B, the die bonding material 4 is applied onthe underside (first main surface) of the semiconductor chip 1 using themetallic mask 3 shown in FIG. 11A. As a result, when die bonding thesemiconductor chip 1, the wet die bonding material 4 spreads over theunderside of the semiconductor chip 1, on the approximately diagonallines of the shape of the semiconductor chip 1, as shown in FIG. 12C.Upon the encapusulation, encapusulating material 11 is encapusulatedbetween semiconductor chip 1 a, except for die bonding material 4, so asto provide a semiconductor device 30 as shown in FIG. 14A.

As shown in FIGS. 13A and 13B, the die bonding material 4 is applied onthe underside (first main surface) of the semiconductor chip 1 using themetallic mask 3 shown in FIG. 11B. As a result, when die bonding thesemiconductor chip 1, the wet die bonding material 4 spreads over theunderside of the semiconductor chip 1, to pass through the center ofsemiconductor chip 1 and an end of the semiconductor chip 1, as shown inFIG. 13C. Upon encapusulation, encapusulating material 11 isencapusulated between semiconductor chip 1 a, 1 b, so as to provide asemiconductor device 30 as shown in FIG. 14B.

By selectively applying the die bonding material 4 on under side ofsemiconductor chip 1, the amount of die bonding material 4 issignificantly reduced compared with applying the die bonding material 4on the entire surface of the underside of semiconductor chip 1.

Note that while the shape of the window formed in the metallic mask 3has been explained in the description of the aforementioned embodiment,a screen printing metallic mask with the same shape to be used forfabricating a semiconductor device is provided according to anotherembodiment. The thickness and material of the metallic mask areselectable based on knowledge of those skilled in the art.

(FIRST EXAMPLE)

A semiconductor device 10 shown in FIG. 4A is fabricated under thefollowing conditions in conformity with the above-described embodiment.

A metallic mask 3 including equally-spaced bobbin-shaped windows is usedas a metallic mask as shown in FIG. 8A. It is assumed that the thicknessof the metallic mask 3 is 20 μm and the material is stainless steel. Anultraviolet curing die bonding material is used as the die bondingmaterials 4 a and 4 b. It is assumed that a 8×8 mm dice-shapedsemiconductor chip 1 with a thickness of 85 μm is used as thesemiconductor chips 1 a and 1 b, and that a 6×6 mm spacer 13 with athickness of 70 μm is used as the spacer 13 a. Moreover, it is assumedthat the thickness of the die bonding materials 4 a and 4 b to beapplied to the semiconductor chips 1 a and 1 b and spacer 13 a isapproximately 15 μm.

The semiconductor chip 1 a with the die bonding material 4 a is mountedon the wiring substrate 6. The wire 12 a is bonded to the semiconductorchip 1 a. Afterwards, the second semiconductor chip 1 b is mounted viathe spacer 13. The die bonding material 4 b having the same width asthat of the spacer 13 a is formed on both sides of the spacer 13 a. Thesemiconductor chip 1 b is bonded with the wire 12 b and encapusulatedwith a encapusulating material 11, resulting in a stacked MCMsemiconductor chip 10 having two semiconductor chips 1 a and 1 b, asshown in FIG. 4A. Note that T (which denotes the thickness of thesemiconductor device or the distance from the top of the wiringsubstrate 6 to the top of the very last wiring layer, and is used in thesecond embodiment and comparative examples 1 and 2) is 285 μm.

(SECOND EXAMPLE)

Except for the number of semiconductor chips being increased from two tofour, a stacked MCP semiconductor device 20 is fabricated in the samemanner as with the first embodiment, as shown in FIG. 4B. The thicknessT of the semiconductor device is 655 μm.

(COMPARATIVE EXAMPLE 1)

The semiconductor device 110 shown in FIG. 8A is fabricated in the samemanner as with the first embodiment except for the die bonding material104 being prepared on the semiconductor chip 101 using a earliertechnology method instead of applying a die bonding material on asemiconductor chip via a metallic mask of the present invention.

A 85 μm thick 6×6 mm spacer is used as the spacer 113. The thickness Tof the semiconductor device is 300 μm.

(COMPARATIVE EXAMPLE 2)

The semiconductor device 120 shown in FIG. 8A is fabricated in the samemanner as with the first embodiment except for the die bonding material104 being prepared on the semiconductor chip 101 using a earliertechnology method instead of applying a die bonding material on asemiconductor chip via a metallic mask of the present invention. A 6×6mm spacer with 85 μm in thickness is used as the spacer 113. Thethickness T of the semiconductor device is 700 μm.

Test results from the first and the second embodiment and thecomparative examples 1 and 2 provide the following findings.

According to comparative example 1, a thick spacer 113 a is needed so asto provide enough clearance between the wire 112 a and the die bondingmaterial 104 a on the semiconductor chip 101 b as shown in FIG. 8A. Onthe other hand, since the first embodiment improves the aforementionedproblem with wiring clearance, the thickness of the spacer 13 a can bereduced. Consequently, according to the first embodiment, anapproximately 15 μm-thick space per single wiring layer corresponding tothe thickness of the die bonding material 4 can be omitted. In thismanner, the first embodiment improves the wiring clearance, which allowsfabrication of a thinner semiconductor device than that of comparativeexample 1 while maintaining the same number of wiring layers.

According to a comparision of thickness T in comparative example 2 andthe second embodiment, the second embodiment can provide a reducedthickness compared to that of comparative example 2 by approximately 45μm. This means that the greater the number of wiring layers, the thinnerthe thickness of the semiconductor device.

1. A method of fabrication a semiconductor device, comprising : mountinga first semiconductor chip on a wiring substrate; bonding a spacerhaving a first main surface and a second main surface oppose to thefirst main surface so that the first main surface contact to the firstsemiconductor chip; and bonding a second semiconductor chip having athird main surface larger than the first main surface, onto the secondmain surface via a layer of a die bonding material selectively formed ona part of the third main surface.
 2. The method of claim 1, furthercomprising: forming recesses in a main surface of a wafer, semiconductorelements are integrated on and in the main surface; bonding a surfaceprotection sheet onto the main surface; and grinding another mainsurface opposing the main surface so as to cut off the secondsemiconductor chip from the wafer.
 3. The method of claim 2, furthercomprising: forming the layer of the die bonding material on a part ofthe third main surface by screen printing; and bonding the secondsemiconductor chip thereto.
 4. The method of claim 2, furthercomprising: selectively applying the layer of the die bonding materialon a region of the third main surface defined by curved lines connectingadjacent apexes of a polygon; wherein the center of each curved lineruns into an inner area of lines connecting adjacent apexes, whichcorrespond to a beginning and the end point of each curved line.
 5. Asemiconductor device comprising: a wiring substrate; a firstsemiconductor chip mounted on the wiring substrate; a spacer having afirst main surface bonded onto the first semiconductor chip and a secondmain surface opposing to the main surface; a die bonding materialdipposed on the second main surface; and a second semiconductor chiphaving a third main surface larger than the first main surface and afourth main surface opposing the third main surface, and having thecenter of the third main surface bonded together with the spacer so thatthe die bonding material is in contact with only a part of the thirdmain surface.